The present invention relates to a surface discharge type plasma display panel and more particularly to a technique for driving an address electrode thereof.
FIG. 56 is a circuit diagram showing a state of address electrode driving of a surface discharge type plasma display panel. Scan electrodes X and Yk intersect an address electrode Aj for one display cell Cjk of the surface discharge type plasma display panel (j, k=1, 2 . . . ).
In such a surface discharge type plasma display panel, there has conventionally been proposed a technique that a negative pulse is not given to the scan electrode Yk but a great positive pulse is given to the address electrode Aj when performing a so-called xe2x80x9cpriming dischargexe2x80x9d in which a history in the display cell Cjk is erased and a space charge is left. The reason is that a positive pulse can be generated more simply and easily than a negative pulse.
A high voltage generating circuit AD1 and an address drive circuit AD2 for switching an output of the high voltage generating circuit AD1 or a ground potential and for outputting the same to the address electrode Aj are provided corresponding to the address electrode Aj. The address drive circuit AD2 comprises switches SW3 and SW4 which are connected in series between the output of the high voltage generating circuit AD1 and the ground potential, and diodes D3 and D4 connected in parallel with the switches SW3 and SW4 respectively.
The scan electrode X is provided with a drive circuit SD3 for generating a voltage to be applied to the scan electrode X. Furthermore, a scanning drive circuit SD1 and a switch circuit SD2 for switching an output of the scanning drive circuit SD1 or a ground potential and for outputting the same to each scan electrode Yk are provided corresponding to the scan electrode Yk.
Such a structure has been described in Japanese Patent Laid-open No. P07-160218A, for example, in which the high voltage generating circuit AD1 and the address drive circuit AD2 are indicated as the reference numerals 233a and 233bj, respectively.
To the address electrode Aj are respectively applied a voltage Vaw for a priming discharge for write preparation (xe2x80x9ca reset periodxe2x80x9d described in the Japanese Patent Laid-open No. P07-160218A), a voltage Va for a write discharge (xe2x80x9can address periodxe2x80x9d described in the Japanese Patent Laid-open No. P07-160218A) and a voltage Vaw for a sustain discharge period (xe2x80x9ca sustain discharge periodxe2x80x9d described in the Japanese Patent Laid-open No. P07-160218A).
For the reset period and the sustain discharge period, a switch SW2 of the high voltage generating circuit AD1 is turned off and a switch SW1 thereof is turned on so that a voltage Vas supported by a Zener diode is added to the voltage Va supplied from a power source and a voltage Vaw(=Va+Vas) is output from the high voltage generating circuit AD1. Then, the switches SW4 and SW3 of the address drive circuit AD2 for all the address electrodes Aj are turned off and on, respectively. Consequently, the voltage Vaw is supplied to all the address electrodes Aj.
However, a rated voltage of an IC constituting the high voltage generating circuit AD1 and the address drive circuit AD2 should be set equal to or higher than a maximum value of a voltage to be used in the above-mentioned procedure. For this reason, the rated voltage of the IC should be equal to or higher than the voltage Vaw(=Va+Vas) which is higher than the voltage Va required for the write discharge and is required for the sustain discharge period.
More specifically, an IC having a high breakdown voltage is required to output a high voltage for the reset period and the sustain discharge period. As a result, a cost is increased. Moreover, since the voltages to be output for the reset period and the sustain discharge period are also influenced by the performance of the IC, a value thereof is limited.
In a conventional method, furthermore, in the case where the switch SW3 on a high arm of the address drive circuit AD2 is turned on to output xe2x80x9cHxe2x80x9d for the write discharge period, a current sometimes flows into the address electrode Aj in a suction direction by the output of the scan electrodes X and Yk.
FIG. 57 is a circuit diagram showing, in detail, a structure of the address drive circuit AD2 illustrated in FIG. 56, in which the display cell Cjk is replaced by an electrically equivalent circuit. There exists an equivalent capacitor CP between the scan electrode Yk and the address electrode Aj. Similarly, the equivalent capacitors exist between the scan electrode X and the address electrode Aj and between the scan electrode X and the scan electrode Yk. The switches SW3 and SW4 of the address drive circuit AD2 are implemented by MOS transistors T1 and T2, respectively.
The address drive circuit AD2 gives xe2x80x9cHxe2x80x9d to the address electrode Aj so that the equivalent capacitor CP is charged. With such charging kept, switches SW5 and SW6 are turned on and off in the switch circuit SD2 for the sustain discharge period, respectively. When the voltage of the scan electrode Yk is changed to xe2x80x9cHxe2x80x9d, the electric potential of the address electrode Aj tries to perform step-up by the equivalent capacitor CP. At this time, the diode D3 of the address drive circuit AD2 causes a current to flow to the power source side for supplying the electric potential Va, thereby preventing the step-up of the voltage.
In this case, if the MOS, transistors T1 and T2 constituting the address drive circuit AD2 are not formed by using a dielectric isolating method but a self-isolating technique, a parasitic transistor is generated. Consequently, the following problem arises.
FIG. 58 is a sectional view showing structures of the MOS transistors T1 and T2 formed by using the self-isolating technique. A PNP transistor T3 is parasitic on the PMOS transistor T1, and a base current of the parasitic transistor flows with a rise in the electric potential of the address electrode Aj. Consequently, a short-circuit current 12 flows from the power source for supplying the electric potential Va to a ground through the transistors T1 and T3. Therefore, there is a possibility that the address drive circuit AD2 might be subjected to a thermal breakdown.
A first aspect of an address electrode driving apparatus for driving an address electrode for a surface discharge type plasma display panel having a plurality of scan electrodes, a plurality of address electrodes which are orthogonal to the scan electrodes, and a display cell formed on each of intersecting points of the scan electrodes and the address electrodes, in accordance with the present invention, is that the apparatus comprises a plurality of drive circuits including a first number of output stages, each output stage having an output terminal provided corresponding to each of the address electrodes and connected thereto, and a first input terminal and a second input terminal, one of which is selectively connected to the output terminal, a first power control circuit for supplying, to the second input terminal, one of a reference potential and a first electric potential which is higher than the reference potential, and a second power control circuit for supplying, to the first input terminal, a second electric potential which is lower than the first electric potential and is higher than the reference potential or connecting the first input terminal to the second input terminal.
A second aspect of the address electrode driving apparatus in accordance with the present invention is that the apparatus of the first aspect further comprises a control circuit for outputting drive data which serves to set the output terminal of the drive circuit to be connected to the first input terminal or the second input terminal, and a plurality of transmitting circuits provided corresponding to each of the address electrodes for transmitting the drive data for the corresponding address electrodes. Each of the transmitting circuits includes a first buffer having an input terminal for inputting the drive data and an output terminal for transmitting the drive data, being connected to a first reference potential point for supplying the reference potential and a first electric potential point for supplying a first source potential which is higher than the reference potential and is lower than the second electric potential, and receiving operating power therefrom, a capacitor having one of terminals connected to the output terminal of the first buffer and the other terminal, and a second buffer having an input terminal connected to the other terminal of the capacitor and an output terminal connected to a corresponding one of the drive circuits, being connected to the second input terminal and a second electric potential point, and receiving operating power therefrom.
A third aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the second aspect, each of the drive circuits further includes a protective diode having a cathode connected to a corresponding one of the address electrodes and an anode connected to the second input terminal.
A fourth aspect of the address electrode driving apparatus in accordance with the present invention is that the apparatus of the third aspect further comprises a third electric potential point to be connected to one of a fourth electric potential point to which a second source potential is supplied and the second input terminal. Each of the transmitting circuits further includes a first diode having an anode connected to the first reference potential point and a cathode connected to the terminal of the capacitor, and a second diode having an anode connected to the other terminal of the capacitor and a cathode connected to the third electric potential point, and the second buffer further includes a protective diode having a cathode connected to the other terminal of the capacitor and an anode connected to the second input terminal.
A fifth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the fourth aspect, the second electric potential point is the third electric potential point.
A sixth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the fourth aspect, the second electric potential point is the fourth electric potential point.
A seventh aspect of the address electrode driving apparatus in accordance with the present inventions is that in the apparatus of the fourth aspect, each of the transmitting circuits further includes a third diode having an anode connected to the terminal of the capacitor and a cathode connected to the first electric potential point.
An eighth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the seventh aspect, the second electric potential point is the third electric potential point.
A ninth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the seventh aspect, the second electric potential point is the fourth electric potential point.
A tenth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the fourth aspect, the first buffer further includes a protective diode having an anode connected to the terminal of the capacitor and a cathode connected to the first electric potential point.
An eleventh aspect of the address electrode driving apparatus in accordance with the present invention is that the apparatus of the fourth aspect further comprises a diode having an anode connected to the fourth electric potential point and a cathode, and a capacitor connected between the cathode of the diode and a second reference potential point acting as a reference of a second source potential to be applied to the fourth electric potential point. The third electric potential point is connected to the fourth electric potential point through the diode.
A twelfth aspect of the address electrode driving apparatus in accordance with the present invention is that the apparatus of the second aspect further comprises a control circuit for outputting drive data which serves to set the output terminal of the drive circuit to be connected to the first input terminal or the second input terminal, and a plurality of transmitting circuits provided corresponding to each of the address electrodes for transmitting the drive data for the corresponding address electrodes. Each of the transmitting circuits includes a first buffer having an input terminal for inputting the drive data and an output terminal for transmitting the drive data, being connected to a first reference potential point for supplying the reference potential and a first electric potential point for supplying a first source potential which is higher than the reference potential and is lower than the second electric potential, and receiving operating power therefrom, a diode having an anode connected to the output terminal of the first buffer and a cathode, and a second buffer having an input terminal connected to the cathode of the diode and an output terminal connected to a corresponding one of the drive circuits, being connected to the second input terminal and a second electric potential point, and receiving operating power therefrom.
A thirteenth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the twelfth aspect, each of the transmitting circuits further includes a resistor provided between the cathode of the diode and the second input terminal.
A fourteenth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the second aspect, the drive circuits further include a second number of data input terminals for inputting the second number of drive data, and the second number of data output terminals for shifting out data given to the data input terminals, and a third number of drive circuits make a set and are connected in series with respect to the data input terminals and the data output terminals.
A fifteenth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the fourteenth aspect, the set of drive circuits have a timing in which the drive data is shifted out from the data input terminal to the data output terminal and a timing in which the drive data given to the data input terminal is latched, the timings being divided into two classes which are different from each other.
A sixteenth aspect of the address electrode driving apparatus in accordance with the present invention is that in the apparatus of the first aspect, the surface discharge type plasma display panel further includes a plurality of other scan electrodes which are orthogonal to the address electrodes, and a predetermined electric potential is applied to the other scan electrodes through a pair of diodes connected in antiparallel with each other.
A first aspect of an address electrode driving method in accordance with the present invention is that the method is applied to a plasma display system comprising a surface discharge type plasma display panel including a plurality of scan electrodes, a plurality of address electrodes which are orthogonal to the scan electrodes, and a display cell formed on each of intersecting points of the scan electrodes and the address electrodes, a plurality of drive circuits including a first number of output stages, each output stage having an output terminal provided corresponding to each of the address electrodes and connected thereto, and a first input terminal and a second input terminal, one of which is selectively connected to the output terminal, a plurality of drive circuits provided corresponding to the address electrodes, each of which has an output terminal connected to a corresponding one of the address electrodes and a first input terminal and a second input terminal, one of which is selectively connected to the output terminal, a control circuit for outputting drive data which serves to set the output terminal of the drive circuit to be connected to the first input terminal or the second input terminal, a first power control circuit for supplying, to the second input terminal, one of a reference potential and a first electric potential which is higher than the reference potential, a second power control circuit for supplying, to the first input terminal, a second electric potential which is lower than the first electric potential and is higher than the reference potential, or for connecting the first input terminal to the second input terminal, a first buffer having an input terminal provided corresponding to each of the address electrodes for inputting the drive data for the corresponding address electrodes, an output terminal for transmitting the drive data, and an output stage having a push-pull structure which is connected in series between a first reference potential point for supplying the reference potential and a first electric potential point for supplying a first source potential which is higher than the reference potential and is lower than the second electric potential, a capacitor having one of terminals connected to the output terminal of the first buffer and the other terminal, a second buffer having an input terminal connected to the other terminal of the capacitor, an output terminal connected to a corresponding one of the drive circuits, and an input stage having a push-pull structure which is connected in series between the second input terminal and a second electric potential point, a first diode having an anode connected to the first reference potential point and a cathode connected to the terminal of the capacitor, and a second diode having a cathode connected to the second electric potential point and an anode connected to the other terminal of the capacitor. The method comprises the steps of (a) for a write preparation period, (a-1) connecting the second electric potential point to the second input terminal, (a-2) connecting the first input terminal to the second input terminal by the second power control circuit, and (a-3) supplying the first electric potential to the second input terminal by the first power control circuit, and then supplying the reference potential, (b) for a write discharge period, (b-1) connecting the second input terminal to the first reference potential point by the first power control circuit, (b-2) supplying the first source potential to the second electric potential point, (b-3) supplying the second electric potential to the first input terminal by the second power control circuit, and (b-4) connecting an output terminal of each of the drive circuits to one of the first input terminal and the second input terminal based on the drive data, and (c) after the write discharge period and before a sustain discharge period, (c-1) connecting the second input terminal to the first reference potential point by the first power control circuit, (c-2) connecting the second electric potential point to the second input terminal, (c-3) connecting the first input terminal to the second input terminal by the second power control circuit, and (c-4) forcedly setting the drive data to a reference potential.
A second aspect of the address electrode driving method in accordance with the present invention is that the method of the first aspect further comprises the step of (a-4) forcedly setting the drive data to xe2x80x9cHxe2x80x9d prior to the step (a-3) for the write preparation period.
A third aspect of the address electrode driving method in accordance with the present invention is that the method of the second aspect further comprises the step of (d) forcedly setting the drive data to xe2x80x9cLxe2x80x9d after the write preparation period and before the write discharge period.
A fourth aspect of an address electrode driving method in accordance with the present invention is that the method is applied to a plasma display system comprising a surface discharge type plasma display panel including a plurality of scan electrodes, a plurality of address electrodes which are orthogonal to the scan electrodes, and a display cell formed on each of intersecting points of the scan electrodes and the address electrodes, a plurality of drive circuits including an output terminal provided corresponding to each of the address electrodes and connected to a corresponding one of the address electrodes, and a first input terminal and a second input terminal, one of which is selectively connected to the output terminal, a control circuit for outputting drive data which serves to set the output terminal of the drive circuit to be connected to the first input terminal or the second input terminal, a first power control circuit for supplying one of a reference potential and a first electric potential which is higher than the reference potential to the second input terminal, and a second power control circuit for supplying, to the first input terminal, a second electric potential which is lower than the first electric potential and is higher than the reference potential or connecting the first input terminal to the second input terminal, a first buffer having an input terminal provided corresponding to each of the address electrodes for inputting the drive data for the corresponding address electrodes, an output terminal for transmitting the drive data, and an output stage having a push-pull structure which is connected in series between a first reference potential point for supplying the reference potential and a first electric potential point for supplying a first source potential that is higher than the reference potential and is lower than the second electric potential, a diode having an anode connected to the output terminal of the first buffer and a cathode, a second buffer having an input terminal connected to the cathode of the diode, an output terminal connected to a corresponding one of the drive circuits, and an input stage having a push-pull structure which is connected in series between the second input terminal and a second electric potential point, and a resistor connected to the second input terminal and the input terminal of the second buffer. The method comprises the steps of (a) for a write preparation period, (a-1) connecting the first input terminal to the second input terminal by the second power control circuit, and (a-2) supplying the first electric potential to the second input terminal by the first power control circuit, and then supplying the reference potential, (b) for a write discharge period, (b-1) connecting the second input terminal to the first reference potential point by the first power control circuit, (b-2) supplying the second electric potential to the first input terminal by the second power control circuit, and (b-3) connecting the output terminals of the drive circuits to one of the first input terminal and the second input terminal based on the drive data, and (c) after the write discharge period and before a sustain discharge period, (c-1) connecting the second input terminal to the first reference potential point by the first power control circuit, and (c-2) connecting the first input terminal to the second input terminal by the second power control circuit.
According to the first aspect of the address electrode driving apparatus in accordance with the present invention, the first power control circuit can supply the reference potential to the second input terminal, and the second power control circuit can supply the first electric potential to the first input terminal. By selectively connecting the output terminal to the first input terminal or the second input terminal in the drive circuit, therefore, a write discharge can be performed for the address electrode in a desirable pattern. On the other hand, the first power control circuit supplies the first electric potential to the second input terminal and the second power control circuit connects the first input terminal to the second input terminal and short-circuits the second input terminal and the output terminal of the drive circuit. Consequently, it is possible to supply the second electric potential to all the address electrodes at once without requiring a breakdown voltage for the second electric potential in the drive circuit. Thus, a self-erase discharge for write preparation can be performed.
According to the second aspect of the address electrode driving apparatus in accordance with the present invention, two buffers for transferring the drive data are employed. The first buffer is isolated from the second input terminal of the drive circuit by the capacitor. Accordingly, even if the first power control circuit supplies the first electric potential to the second input terminal of the drive circuit, the first buffer is isolated from the first electric potential. Consequently, the control circuit can also be protected.
According to the third aspect of the address electrode driving apparatus in accordance with the present invention, in the case where the first electric potential is applied to the second input terminal, it is given to the address electrode through the protective diode. Consequently, the self-erase discharge can be caused.
According to the fourth to sixth aspects of the address electrode driving apparatus in accordance with the present invention, the capacitor charged by application of the first electric potential to the second input terminal can be discharged by supplying the reference potential to the second input terminal and connecting the third electric potential point to the second input terminal by means of the first power control circuit. At the time of the write discharge, even if the first buffer is changed between xe2x80x9cLxe2x80x9d and xe2x80x9cHxe2x80x9d, the charge and discharge of the capacitor can be quickly performed by supplying the reference potential to the second input terminal and connecting the fourth electric potential point to the third electric potential point by means of the first power control circuit. Therefore, the drive data can be transmitted to the second buffer. Furthermore, after the write discharge is completed, the first power control circuit supplies the reference potential to the second input terminal and connects the first reference potential point to the third electric potential point, thereby discharging the capacitor whether the first buffer outputs xe2x80x9cLxe2x80x9d to charge the capacitor or outputs xe2x80x9cHxe2x80x9d to charge the capacitor. Consequently, a sustain discharge is not affected.
According to the seventh to tenth aspects of the address electrode driving apparatus in accordance with the present invention, in the case where the first electric potential is to be applied to the address electrode, the first buffer can be protected from the step-up of a voltage caused by the capacitor even if the first buffer is caused to output xe2x80x9cHxe2x80x9d in order to rapidly rise.
According to the twelfth aspect of the address electrode driving apparatus in accordance with the present invention, the electric potential which is lower than the second source potential by a forward voltage of the diode is applied to the third electric potential point. Therefore, the capacitor is not charged based on the forward voltage of the second diode of the transmitting circuit.
According to the twelfth aspect of the address electrode driving apparatus in accordance with the present invention, two buffers for transferring the drive data are employed. Even if the first electric potential is applied to the second input terminal, the diode is reversibly biased. Therefore, the first buffer is isolated from the first electric potential. Consequently, the control circuit can also be protected.
According to the thirteenth aspect of the address electrode driving apparatus in accordance with the present invention, even if Hxe2x80x9d is input to the first buffer and the diode is forward biased to cause a forward current to flow when the self-erase discharge is completed, a magnitude of the forward current can be limited by the resistor and the first buffer can be protected from a fluctuation in the electric potential of the second input terminal. Furthermore, if the drive data is changed from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d for the write discharge period, electric charges held in an input capacity of the second buffer can be discharged through the resistor.
According to the fourteenth aspect of the address electrode driving apparatus in accordance with the present invention, since it is sufficient that the transmitting circuit transmits the drive data every third number, a structure thereof can be simplified.
According to the fifteenth aspect of the address electrode driving apparatus in accordance with the present invention, since it is sufficient that the transmitting circuit transmits the drive data every 2xc3x97the third number of output circuits, a structure thereof can further be simplified.
According to the sixteenth aspect of the address electrode driving apparatus in accordance with the present invention, the electric potential of the other scan electrode is not raised above a predetermined electric potential even if it tries to perform step-up by an equivalent capacitor in the display cell.
According to the first aspect of the address electrode driving method in accordance with the present invention, by the function of the capacitor, the second electric potential can be applied to all the address electrodes at once for the write preparation period without requiring a breakdown voltage for the second electric potential in the drive circuit. Consequently, a self-erase discharge can be performed. The capacitor charged by a write discharge is discharged by the output stage of the first buffer and the second diode or by the input stage of the second buffer and the first diode at the step (c) before the sustain discharge period.
According to the second aspect of the address electrode driving method in accordance with the present invention, the capacitor can be charged in advance to raise an electric potential on the other terminal above an electric potential on the one of terminals. Therefore, it is possible to enhance a speed at which the second input terminal can rise to the first electric potential at the step (a-3).
According to the third aspect of the address electrode driving method in accordance with the present invention, the capacitor charged at the step (a-4) is discharged. Consequently, it is possible to avoid affecting the write discharge period.
According to the fourth aspect of the address electrode driving method in accordance with the present invention, by the function of the diode, the second electric potential can be supplied to all the address electrodes at once for the write preparation period without requiring a breakdown voltage for the second electric potential in the drive circuit. Consequently, the self-erase discharge can be performed. By the function of the resistor, a current flowing in the first buffer means is suppressed if the drive data is changed from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d for the write discharge period, and electric charges stored in the input stage of the second buffer are discharged when the drive data is changed from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d.
In order to solve the above-mentioned problems, it is an object of the present invention to freely set a high voltage output for a priming discharge period and a sustain discharge period without increasing a rating required for an IC having an address driver.